1. Field of the Invention
The present invention relates to semiconductor memory devices and, more specifically, to sense amplifier circuits for dynamic random access memory devices (DRAMs).
2. Discussion of Related Art
Memory devices such as dynamic random access memories comprise an array of individual memory cells. Typically, each DRAM memory cell comprises a capacitor for holding a charge and an access transistor for accessing the capacitor charge. The charge is representative of a data bit and can be either high voltage or low voltage (representing, e.g., a logical "1" or a logical "0," respectively). Data can be stored in memory during write operations or read from memory during read operations. Refresh, read, and write operations in present-day DRAMs are typically performed for all cells in one row simultaneously. Data is read from memory by activating a row, referred to as a word line, which couples all memory cells corresponding to that row to digit or bit lines which define the columns of the array. When a particular word line is activated, sense amplifiers detect and amplify the data by measuring the potential difference corresponding to the content of the memory cell connected to the activated word line. The operation of DRAM sense amplifiers is described, for example, in U.S. Pat. Nos. 5, 627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc. and incorporated by reference herein.
DRAM memory devices are called dynamic because data is stored only temporarily and must be continually rewritten or refreshed. Data is stored in the form of charged capacitors and is necessarily temporary because of parasitic leak currents in current integrated circuits (ICs). Because the capacitor charge decays away in a finite interval of time (in the order of milliseconds), periodic refresh operations which include a special read cycle followed by rewriting of the same data are necessary at regular intervals for the DRAM to retain its "memory." The advantageous attribute of DRAMs that offsets its transitory nature is its small size. Memory cell sizes in current DRAMs range from 450 .mu.m.sup.2 in the 16,384.times.1 bit DRAM to 160 .mu.m.sup.2 in the more advanced 65,536.times.1 bit DRAM.
Historically, DRAMs have had relatively large memory cells with large supply voltages. Over the last several decades, however, the densities of DRAMs have, on average, doubled every year and a half. As is well known in the art, semiconductor memories such as DRAMs are generally mass produced by fabricating hundreds of identical circuit patterns on a single semiconductor wafer, which is subsequently cut into hundreds of identical dies or chips. The advantages of building integrated circuits with smaller individual circuit elements so that more and more circuitry may be packed on a single chip are well-known. Electric equipment, for example, becomes less bulky, reliability is improved by reducing the number of solder plug connections, assembly and packaging costs are minimized, and circuit performance is improved, particularly at higher clock speeds.
The rapid increase in bit density is the result of intensive technical efforts by design and process engineers, but decreased size and increased densities of DRAMs also have associated problems. One problem is that the smaller size of individual cells leads to reducing the size of the individual electrical components in the cells, and consequently to smaller electrical signals. The magnitude of the storage capacitor of each cell decreases as well. Furthermore, as more and more individual storage cells are placed onto a single chip, the length of the column lines connecting the individual cells to the sense amplifiers becomes longer and the capacitance associated with the lines becomes larger. This means that the signal transferred to the column line from an individual cell will become even smaller as the capacitance of the line absorbs the charge, and further that the time for developing a useful signal level on the line will increase. The combination of small signals and longer lines with large associated capacitance results in long RC intervals of time for useful signal levels to rise on the lines. These RC intervals, which may be in the order of 7-9 nanoseconds, are actually "dead time," during which a word line signal propagates from the front edge to the back edge of the word line.
All of these factors reduce the magnitude of the data signal which exists on a digit line. This decrease, when coupled with the fact that the memory array produces noise which disturbs small signal detection, may lead to difficulty in properly sensing a bit value. One way of improving proper memory cell sensing is to reduce memory array noise.
A major factor which contributes to a deterioration in the ability to sense a bit value in present-day DRAMs is that all sense amplifiers associated with a particular word line are activated at the same time. In a 1-Megabit DRAM, for example, which is refreshed at 512 cycles per period, there are 2048 sense amplifiers which are activated at the same time during an active cycle. The voltage supply to the chip sees a very large current spike in a short time period, which generates memory array noise due to the fact that the current consumed by the sense amplifiers is increased rapidly, as shown by peak value Ia in FIG. 4(d). The rapid increase in the consumption of the current Is causes the supply voltage to drop while at the same time causing memory array noise.
In high density memory design, therefore, it is critical that the DRAM sense amplifiers reliably detect the low-level signals. As is well known, however, speed is also an important factor in semiconductor memory devices. Thus, while high quality sensing in present-day DRAMs is imperative, it must not be accompanied by a decrease in the sensing speed. The performance of DRAMs would be enhanced by reducing the access time of a DRAM, thereby speeding up its operation.
A technique for reducing memory array noise associated with the DRAM peak current produced by simultaneous activation of all sense amplifiers linked to a particular word line is described in U.S. Pat. No. 4,916,671 to Ichiguchi. That technique is based on activating the sense amplifiers associated with a particular active word line for selected columns only, thereby resulting in spreading out the peak current and reducing DRAM noise. This method, however, is based on advance knowledge of the particular column address of the memory cell within the word line which is being activated, so that the corresponding sense amplifiers may be activated at the same time. Another corresponding section of sense amplifiers is activated upon selection of the next memory cell with known column address. The requirement of advance knowledge of the column address, however, may lead to significantly delaying the operation of the DRAM, especially in the case where column addresses are selected more quickly than row addresses.
Another technique for reducing memory array noise associated with the DRAM peak current produced by simultaneous activation of all sense amplifiers linked to a particular word line is described in U.S. Pat. No. 5,343,433 to Duvvury et al. This technique relies on determining the peak current draw for a whole bank of sense amplifiers and selectively turning on particular columns based, as in the method described above, upon advance knowledge of column addresses, thereby reducing the peak current and the DRAM noise.
None of the above patents, however, solves the problem of reducing DRAM noise and consequently improving DRAM sensitivity by reducing the peak current in DRAM sense amplifiers while increasing DRAM speed of operation.
There is a need, therefore, to improve the sensing qualities of DRAMs, particularly high-speed, low power DRAMs, by reducing the peak current and associated noise produced by the simultaneous activation of numerous sense amplifiers associated with an active word line, while at the same time increasing the speed of operation of the DRAM.